CD40109 CMOS Quad Low-to-High Voltage Level Shifter IC DIP-16 Package

CD40109 contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = V _CC and logical 0 = V _SS to a high-voltage output signal (E, F, G, H) with logical 1 = V _DD and logical 0 = V _SS .

The RCA-CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (V _DD ) before the application of either the low-voltage supply (V _CC ) or the input signals. There are no restrictions on the sequence of application of V _DD , V _CC , or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between V _SS and at least 0.7 V _CC ; V _CC may exceed V _DD , and input signals may exceed V _CC and V _DD . When operated in the mode V _CC > V _DD , the CD40109 will operate as a high-to-low level-shifter.

The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.

Features:-

• Qualified for Automotive Applications
• Independent of Power Supply Sequence Considerations
  • V _CC Can Exceed V _DD
  • Input Signals can Exceed Both V _CC and V _DD
• Up and Down Level-Shifting Capability
• Three-State Outputs With Separate Enable Controls
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current:
  • 1 µA at 18 V Over Full Package-Temperature Range
  • 100 nA at 18 V and 25°C
• Noise Margin (Full Package-Temperature Range):
  • 1 V at V _CC = 5 V, V _DD = 10 V
  • 2 V at V _CC = 10 V, V _DD = 15 V
• 5-V, 10-V, and 15-V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard specifications for Description of ’B’ Series CMOS Devices"
• Latch-Up Performance Meets 50 mA per JESD 78, Class I
• APPLICATIONS
  • High-or-Low Level-Shifting With Three-State Outputs for Unidirectional or Bidirectional Bussing
  • Isolation of Logic Subsystem Using Separate Power Supplies from Supply Sequencing, Supply Loss, and Supply Regulation Considerations.

Specifications:-

Related Documents:-

CD40109 IC Datasheet